Efficient Parallel Implementation of Matrix Multiplication for Lattice-Based Cryptography on Modern ARM Processor
نویسندگان
چکیده
منابع مشابه
Generalizing Matrix Multiplication for Efficient Computations on Modern Computers
Recent advances in computing allow taking new look at matrix multiplication, where the key ideas are: decreasing interest in recursion, development of processors with thousands (potentially millions) of processing units, and influences from the Algebraic Path Problems. In this context, we propose a generalized matrix-matrix multiply-add (MMA) operation and illustrate its usability. Furthermore,...
متن کاملParallel Implementation of Interval Matrix Multiplication
Two main and not necessarily compatible objectives when implementing the product of two dense matrices with interval coefficients are accuracy and efficiency. In this work, we focus on an implementation on multicore architectures. One direction successfully explored to gain performance in execution time is the representation of intervals by their midpoints and radii rather than the classical re...
متن کاملEfficient Implementation of Interval Matrix Multiplication
The straightforward implementation of interval matrix product suffers from poor efficiency, far from the performances of highly optimized floating-point implementations. In this paper, we show how to reduce the interval matrix multiplication to 9 floating-point matrix products for performance issues without sacrificing the quality of the result. We show that, compared to the straightforward imp...
متن کاملTowards efficient lattice-based cryptography
One essential quest in cryptography is the search for hard instances of a given computational problem that is known to be hard in the worst-case. In lattice cryptography we are in the unique situation that we have found a way of picking random instances which are at least as hard as well-studied lattice problems in the worst-case. At the same time, no attack running in subexponential time is kn...
متن کاملAn Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Security and Communication Networks
سال: 2018
ISSN: 1939-0114,1939-0122
DOI: 10.1155/2018/7012056